搜索资源列表
Intel8251
- 用VHDL实现Intel 8251的UART功能-Intel 8251 with VHDL realization of the UART Function
uart
- UART串口的verilog源代码，完全正确-UART serial Verilog source code, completely correct ...........
test_uart
- uart VHDL code : include tx,rx,parity bit control
UART
- 带有自适应功能的UART，是用VERILOG编写的源码，包括测试文件，与大家分享-Adaptive function with UART, are prepared using VERILOG source code, including test papers, to share with you
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
UART
- UART接口的源码测试程序、Verilog语言编写-UART
uart
- this file contains verilog code of uart file
uart_txd
- 基于verilog hdl的UART串口发送子程序。-Verilog hdl a UART-based serial port to send subroutine.
Transmitter
- UART Transmitter Verilog Code
Receiver
- UART Receiver Verilog Code
uart
- 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove
uart
- 使用VERILOG实现自己定以的UART算法，只要自己看懂了，再修给下下就可以使用了-VERILOG use to achieve their own set of UART algorithm, as long as my understood, and then repair to the next can be used under
RD1011_rev01.2
- 采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog t
uart
- 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a
uart
- i like verilog VHDL and system Verilog
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
MCU_FPGA_Interface
- msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
xapp345_verilog
- IrDA & UART Design (Verilog)